Altera RapidIO MegaCore Function - Manual (Page 151)

Chapter 6: Software Interface 6–19
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Refer to “Port-Write Processor” on page 4–32 for information about using these
registers to transmit a port-write.
Receive Port-Write Registers
Table 6–36 through Table 6–38 describe the receive port-write registers.
Refer to “Port-Write Reception Module” on page 4–65 for information about receiving
port write MAINTENANCE packets.
Table 6–33. Tx Port Write Control—Offset: 0x10200
Field Bits Access Function Default
LARGE_DESTINATION_ID
(MSB)
[31:24]
RO Reserved if the system does not support 16-bit device ID.
8'h0
RW
MSB of the Destination ID if the system supports 16-bit
device ID.
DESTINATION_ID [23:16] RW Destination ID 8'h0
RSRV [15:8] RO Reserved 8'h00
PRIORITY [7:6] RW
Request packet’s priority.
2’b11 is not a valid value for the priority field. An attempt
to write 2’b11 to this field is overwritten as 2’b10.
2'b00
SIZE [5:2] RW
Packet payload size in number of double words. If set to 0,
the payload size is single word. If size is set to a value
larger than 8, the payload size is 8 double words (64 bytes).
4'h0
RSRV [1] RO Reserved 1'b0
PACKET_READY [0] RW
Write 1 to start transmitting the port-write request. This bit
is cleared internally after the packet has been transferred to
the Transport layer to be forwarded to the Physical layer for
transmission.
1'b0
Table 6–34. Tx Port Write Status—Offset: 0x10204
Field Bits Access Function Default
RSRV [31:0] RO Reserved 31'h0
Table 6–35. Tx Port Write Buffer n—Offset: 0x10210 – 0x1024C
Field Bits Access Function Default
PORT_WRITE_DATA_n [31:0] RW
Port-write data. This buffer is implemented in memory and is
not initialized at reset.
32'hx
Table 6–36. Rx Port Write Control—Offset: 0x10250
Field Bits Access Function Default
RSRV [31:2] RO Reserved 30'h0
CLEAR_BUFFER [1] RW Clear port-write buffer. Write 1 to activate. Always read 0. 1'b0
PORT_WRITE_ENA [0] RW
Port-write enable. If set to 1, port-write packets are accepted.
If set to 0, port-write packets are dropped.
1'b1