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Is set, Table 6–47 – Altera RapidIO MegaCore Function User Manual

Page 155

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Chapter 6: Software Interface

6–23

Transport and Logical Layer Registers

August 2014

Altera Corporation

RapidIO MegaCore Function

User Guide

WRITE_OUT_OF_BOUNDS

[1]

RW1C

Write request address out of bounds. Asserted when the
Avalon-MM address does not fall within any enabled
address mapping windows.

1'b0

READ_OUT_OF_BOUNDS

[0]

RW1C

Read request address out of bounds.

Asserted when the Avalon-MM address does not fall
within any enabled address mapping windows.

1'b0

Table 6–46. Input/Output Slave Interrupt—Offset: 0x10500 (Part 2 of 2)

Field

Bits

Access

Function

Default

Table 6–47. Input/Output Slave Interrupt Enable—Offset: 0x10504

Field

Bits

Access

Function

Default

RSRV

[31:5]

RO

Reserved

27'h0

NWRITE_RS_COMPLETED

[4]

RW

NWRITE_Rs-completed field enable.

1'b0

INVALID_WRITE_BYTEENABLE

[3]

RW

Write byte enable invalid interrupt enable

1'b0

INVALID_WRITE_BURSTCOUNT

[2]

RW

Write burst count invalid interrupt enable

1'b0

WRITE_OUT_OF_BOUNDS

[1]

RW

Write request address out of bounds interrupt enable

1'b0

READ_OUT_OF_BOUNDS

[0]

RW

Read request address out of bounds interrupt enable

1'b0

Table 6–48. Input/Output Slave Pending NWRITE_R Transactions—Offset: 0x10508

Field

Bits

Access

Function

Default

RSRV

[31:5]

RO

Reserved

27'h0

PENDING_NWRITE_RS

[4:0]

RO

Number of pending NWRITE_R write requests that
have been initiated in the I/O Avalon-MM slave Logical
layer module but have not yet completed. The value in
this field might update only after a delay of 8 Avalon
clock cycles after the start of the write burst on the
Avalon-MM interface.

5'b0

Table 6–49. Input/Output Slave Avalon-MM Write Transactions—Offset: 0x1050C

Field

Bits

Access

Function

Default

RSRV

[31:16]

RO

Reserved

16'h0

STARTED_WRITES

[15:0]

RO

Number of write transfers initiated on Avalon-MM
Input/Output Slave port so far. Count increments on
first system clock cycle in which the io_s_wr_write
and io_s_wr_chipselect signals are asserted and
the io_s_wr_waitrequest signal is not asserted.
This counter rolls over to 0 after its maximum value.

16'b0