Altera RapidIO MegaCore Function - Manual (Page 134)

6–2 Chapter 6: Software Interface
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
Table 6–1 lists the access codes used to describe the type of register bits.
Table 6–2 lists the CAR, CSR and all the registers in the extended features
implementation defined address spaces. The doorbell registers are listed in Table 6–57
on page 6–26 .
Table 6–1. Register Access Codes
Code Description
RW Read/write
RO Read-only
RW1C Read/write 1 to clear
RW0S Read/write 0 to set
RTC Read to clear
RTS Read to set
RTCW Read to clear/write
RTSW Read to set/write
RWTC Read/write any value to clear
RWTS Read/write any value to set
RWSC Read/write self-clearing
RWSS Read/write self-setting
UR0 Unused bits/read as 0
UR1 Unused bits/read as 1
Table 6–2. Memory Map (Part 1 of 3)
Address Name Used by
Capability Registers (CARs)
0x0 Device Identity
These CARs are not used by any of the internal modules.
They do not affect the functionality of the RapidIO IP
core. These registers are all Read-Only. Their values are
set using the RapidIO parameter editor when generating
the IP core. These registers inform either a local
processor or a processor on a remote end about the IP
core's capabilities.
0x4 Device Information
0x8 Assembly Identity
0xC Assembly Information
0x10 Processing Element Features
0x14 Switch Port Information
0x18 Source Operations
0x1C Destination Operations
Command and Status Registers (CSRs)
0x4C
Processing Element Logical
layer Control
Input/Output Slave Logical layer
0x58
Local Configuration Space Base
Address 0
Input/Output Master Logical layer
0x5C
Local Configuration Space Base
Address 1
Input/Output Master Logical layer
0x60 Base Device ID
Transport layer for routing or filtering. Input/Output
Slave Logical layer