Altera RapidIO MegaCore Function - Manual (Page 112)

4–66 Chapter 4: Functional Description
Error Detection and Management
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
■ Illegal Transaction Decode is declared for malformed received response packets
occurring from any of the following events:
■ NREAD or NWRITE_R response packet with status not DONE nor ERROR.
■ NWRITE_R response packet with payload or with a transaction type indicating
the presence of a payload.
■ NREAD response packet without payload, with incorrect payload size, or with a
transaction type indicating absence of payload.
Registers in the Implementation Defined Space
The I/O Avalon-MM slave module defines the Input/Output slave interrupt
registers with the following bits. For details on when these bits are set, refer to their
descriptions in
Table 6–46 on page 6–22 .
■ INVALID_WRITE_BYTEENABLE
■ INVALID_WRITE_BURSTCOUNT
■ WRITE_OUT_OF_BOUNDS
■ READ_OUT_OF_BOUNDS
When any of these bits are set, the system interrupt signal sys_mnt_s_irq is also
asserted if the corresponding bit in the Input/Output Slave Interrupt Enable
register (
Table 6–47 on page 6–23 ) is set.
The Avalon-MM Slave Interface's Error Indication Signal
The io_s_rd_readerror output is asserted when a response with ERROR status is
received for an NREAD request packet, when an NREAD request times out, or when the
Avalon-MM address falls outside of the enabled address mapping window. As
required by the Avalon-MM interface specification, a burst in which the
io_s_rd_readerror
signal is asserted completes despite the error signal assertion.
Input/Output Avalon-MM Master
The I/O Avalon-MM master module processes the request packets that it receives and
generates response packets when required. Anomalies are reported through one or
both of the following two channels:
■ Standard error management registers
■ Response packets with ERROR status
Standard Error Management Registers
The following two standard defined error types can be declared by the
I/O Avalon-MM master module. The corresponding bits are then set and the required
packet information is captured in the appropriate error management registers.
■ Unsupported Transaction is declared when a request packet carries a transaction
type that is not supported in the Destination Operations CAR ( Table 6–19 on
page 6–14 ), whether an ATOMIC transaction type, a reserved transaction type, or an
implementation defined transaction type.