Altera RapidIO MegaCore Function - Manual (Page 168)

7–6 Chapter 7: Testbenches
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
1 The Avalon-MM write address must map into Input/Output Slave Window 0.
However, in this example the window is set to cover the entire Avalon-MM address
space by setting the mask to all zeros.
The testbench generates a predetermined series of burst writes across the Avalon-MM
slave I/O interface on the DUT. These write bursts are each converted to an SWRITE
request packet sent on the RapidIO serial interface. Because Streaming Writes only
support bursts that are multiples of a double word (multiple of 8 bytes), the testbench
cycles from 8 to MAX_WRITTEN_BYTES in steps of 8 bytes. Two tasks carry out the burst
writes, rw_addr_data and rw_data. The rw_addr_data task initiates the burst by
providing the address, burstcount, and the content of the first data word, and the
rw_data
task completes the remainder of the burst.
At the sister_rio module, the SWRITE request packets are received and translated into
Avalon-MM transactions that are presented across the Input/Output master
Avalon-MM interface. The testbench calls the task read_writedata of the
sister_bfm_io_write_slave. The task captures the written data.
The written data is then checked against the expected value by running an expect
task. After completing the SWRITE tests, the testbench performs NWRITE_R operations.
NWRITE_R Transactions
To perform NWRITE_R operations, one register in the IP core must be reconfigured as
shown in
Table 7–3 .
With the setting in Table 7–3 , any write operation presented across the Input/Output
Avalon-MM slave module's Avalon-MM write interface is translated to a RapidIO
NWRITE_R
transaction. The Avalon-MM write address must map to the range specified
for the I/O Slave window 0.
To initialize testing of the new NWRITE_R completion indication feature, the test first
checks that the PENDING_NWRITE_RS field of the Input/Output Slave Pending
NWRITE_R Transactions
register has value 0, that the NWRITE_RS_COMPLETED field of
the Input/Output Slave Interrupt Enable register is set, and that the
NWRITE_RS_COMPLETED
field of the Input/Output Slave Interrupt register is clear,
before setting the Input/Output Slave Mapping Window 0 Control register and
starting the sequence of NWRITE_R transactions.
Table 7–3. NWRITE_R Transactions
Module
Register
Address
Name Value Description
rio 0x1040C
Input/Output Slave
Mapping Window 0
Control
32'h0055_0001
or 32'h5555_0001
Sets the DESTINATION_ID for outgoing
transactions to the value 0x55 or 0x5555,
depending on the device ID width of the
sister_rio. This value matches the base
device ID of the sister_rio module. Enables
NWRITE_R
operations.