Port-write processor, Port-write processor –32 – Altera RapidIO MegaCore Function User Manual
Page 78
4–32
Chapter 4: Functional Description
Logical Layer Modules
RapidIO MegaCore Function
August 2014
Altera Corporation
User Guide
■
rdsize/wrsize
■
wdptr
■
config_offset
■
payload
The Maintenance module only supports single 32-bit word transfers, that is, rdsize
and wrsize = 4’b1000; other values cause an error response packet to be sent.
The wdptr and config_offset values are used to generate the Avalon-MM address.
The following expression is used to derive the address:
mnt_m_address
= {rx_base, config_offset, wdptr, 2'b00}
where rx_base is the value programmed in the Rx Maintenance Mapping register at
location 0x10088 (
).
The payload is presented on the mnt_m_writedata[31:0] bus.
Port-Write Processor
The port-write processor performs the following tasks:
■
Composes the RapidIO logical header of a MAINTENANCE port-write request
packet.
■
Presents the port-write request packet to the Transport layer for transmission.
■
Processes port-write request packets received from a remote device.
■
Alerts the user of a received port-write using the sys_mnt_s_irq signal.
The port-write processor is controlled through the use of the registers that are
described in the following sections:
■
“Transmit Port-Write Registers” on page 6–18
■
“Receive Port-Write Registers” on page 6–19
Port-Write Transmission
To send a port-write to a remote device, you must program the transmit port-write
control and data registers. The Tx Port Write Control register is described in
and the Tx Port Write Buffer is described in
. These registers are accessed using the System Maintenance Avalon-MM
slave interface. The following header fields are supplied by the values stored at the Tx
Port
Write Control register:
■
DESTINATION_ID
■
priority
■
wrsize
The other fields of the MAINTENANCE port-write packet are assigned as follows. The
ftype
is assigned a value of 4'b1000 and the ttype field is assigned a value of
4'b0100
. The wdptr and wrsize fields of the transmitted packet are calculated from
the size of the payload to be sent as defined by the size field of the Tx Port Write
Control
register. The source_tid and config_offset are reserved and set to zero.