Altera RapidIO MegaCore Function - Manual (Page 187)

August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
A. Initialization Sequence
This appendix describes the most basic initialization sequence for a RapidIO system
that contains two RapidIO IP cores connected through their RapidIO interfaces.
To initialize the system, perform these steps:
1. Read the Port 0 Error and Status (ERRSTAT) Command and Status register
(CSR) (0x00158) of the first RapidIO IP core to confirm port initialization.
2. Set the following registers in the first RapidIO IP core:
a. To set the base ID of the device to 0x01, set the DEVICE_ID field (bits 23:16) or
the LARGE_DEVICE_ID field (bits 15:0) of the Base Device ID register (0x00060)
to 0x1.
b. To allow request packets to be issued, write 1 to the ENA field (bit 30) of the Port
General Control CSR (0x13C).
c. To set the destination ID of outgoing maintenance request packets to 0x02, set
the DESTINATION_ID field (bits 23:16) or the combined {LARGE_DESTINATION_ID
(MSB)
, DESTINATION_ID} fields (bits 31:16) of the Tx Maintenance Window 0
Control register (0x1010C) to 0x02.
d. To enable an all-encompassing address mapping window for the maintenance
module, write 1’b1 to the WEN field (bit 2) of the Tx Maintenance Window 0
Mask
register (0x10104).
3. Set the following registers in the second RapidIO IP core:
a. To set the base ID of the device to 0x02, set the DEVICE_ID field (bits 23:16) or
the LARGE_DEVICE_ID field (bits 15:0) of the Base Device ID register (0x00060)
to 0x02.
b. To allow request packets to be issued, write 1’b1 to the ENA field (bit 30) of the
Port General Control CSR (0x13C).
c. To set the destination ID of outgoing maintenance packets to 0x0, set the
DESTINATION_ID field (bits 23:16) or the combined {LARGE_DESTINATION_ID
(MSB) , DESTINATION_ID} fields (bits 31:16) of the Tx Maintenance Window 0
Control register (0x1010C) to 0x0.
d. To enable an all-encompassing address mapping window for the maintenance
module, write 1’b1 to the WEN field (bit 2) of the Tx Maintenance Window 0
Mask
register (0x10104).
These register settings allow one RapidIO IP core to remotely access the other
RapidIO IP core.
To access the registers, the system requires an Avalon-MM master, for example a
Nios II processor. The Avalon-MM master can program these registers.
You can use the Qsys system integration tool, available with the Quartus II software,
to rapidly and easily build and evaluate your RapidIO system.