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Physical layer architecture, Physical layer architecture –11, Error management – Altera RapidIO MegaCore Function User Manual

Page 57: Clock decoupling, Fifo buffer with level output port, Adjustable buffer sizes (4 kbytes to 32 kbytes)

Physical layer architecture, Physical layer architecture –11, Error management | Clock decoupling, Fifo buffer with level output port, Adjustable buffer sizes (4 kbytes to 32 kbytes) | Altera RapidIO MegaCore Function User Manual | Page 57 / 198 Physical layer architecture, Physical layer architecture –11, Error management | Clock decoupling, Fifo buffer with level output port, Adjustable buffer sizes (4 kbytes to 32 kbytes) | Altera RapidIO MegaCore Function User Manual | Page 57 / 198
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