Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 98
Registers
DFFS
Speedster22i Macro Cell Library
PAGE 82
Table 2-52: Function Table
Inputs
Output
sn
d
ck
q
when sr_assertion = “unclocked’
Table 2-53: Function Table
Inputs
Output
sn
d
ck
q
when sr_assertion = “clocked’
Verilog Instantiation Template
DFFS #(.init(1’b1))
instance_name
(.q(user_out),
.d(user_din),
.sn(user_set),
.ck(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFS_instance_name : DFFS
generic map (
init => ‘1’)
port map (q => user_out,
d => user_din,
sn => user_set,
ck => user_clock);
0
X
1
1
X
X
Hold
1
0
0
1
1
1
0
X
X
1
1
X
X
Hold
1
0
0
1
1
1