Achronix Speedster22i User Macro Guide - Manual (Page 210)

PLL/DLL Clock Generators ACX_CLKGEN
Speedster Macro Cell Library www.achronix.com PAGE 193
high_cnt2 The output synthesizer divides the PLL output clock by
'high_cnt2 + low_cnt2'. The ratio of high_cnt2 to
'high_cnt2 + low_cnt2' determines the output duty
cycle.
10’h000-10’h3FF 10’h0
low_cnt2 If set to 0, the output synthesizer is bypassed. Other-
wise, the output synthesizer divides the PLL output
clock by 'high_cnt2 + low_cnt2'. The ratio of high_cnt2
to 'high_cnt2 + low_cnt2' determines the output duty
cycle.
10’h000-10’h3FF 10’h0
high_cnt3 The output synthesizer divides the PLL output clock by
'high_cnt3 + low_cnt3'. The ratio of high_cnt3 to
low_cnt3 determines the output duty cycle.
10’h000-10’h3FF 10’h0
low_cnt3 The output synthesizer divides the PLL output clock by
'high_cnt3 + low_cnt3'. The ratio of high_cnt3 to
'high_cnt3 + low_cnt3' determines the output duty
cycle.
10’h000-10’h3FF 10’h0
half_cycle0 If set to 1, it extends the high pulse width of clkout[0] by
1/2 the clkout[0] cycle.
1’b0,1’b1 1’b0
half_cycle1 If set to 1, it extends the high pulse width of clkout[1] by
1/2 the clkout[1] cycle.
1’b0,1’b1 1’b0
half_cycle2 If set to 1, it extends the high pulse width of clkout[2] by
1/2 the clkout[2] cycle.
1’b0,1’b1 1’b0
half_cycle3 If set to 1, it extends the high pulse width of clkout[3] by
1/2 the clkout[3] cycle.
1’b0,1’b1 1’b0
clken_out0 Clkout[0] Clock Gating Enable.
0: Disable core_clken[0] input.
1: Enable core_clken[0] input.
1’b0,1’b1 1’b0
clken_out1 Clkout[1] Clock Gating Enable.
0: Disable core_clken[1] input.
1: Enable core_clken[1] input.
1’b0,1’b1 1’b0
clken_out2 Clkout[2] Clock Gating Enable.
0: Disable core_clken[2] input.
1: Enable core_clken[2] input.
1’b0,1’b1 1’b0
clken_out3 Clkout[3] Clock Gating Enable.
0: Disable core_clken[3] input.
1: Enable core_clken[3] input.
1’b0,1’b1 1’b0
Parameter Description Defined Values
Default
Value