Table - table 2-12: function table, Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 72
Registers
DFFEP
Speedster22i Macro Cell Library
PAGE 56
Table 2-12: Function Table
Inputs
Output
pn
ce
d
ck
q
Verilog Instantiation Template
DFFEP #(.init(1’b1))
instance_name
(.q(user_out),
.d(user_din),
.pn(user_preset),
.ce(user_clock_enable),
.ck(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFEP_instance_name : DFFEP
generic map ( init => ‘1’)
port map (q => user_out,
d => user_din,
pn => user_preset,
ce => user_clock_enable,
ck => user_clock);
X
0
X
X
Hold
0
1
X
1
1
1
0
0
1
1
1
1