Achronix Speedster22i User Macro Guide - Manual (Page 95)

Registers DFFR
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 79
DFFR
Positive Clock Edge D-Type Register with Asynchronous Reset
rn
d
ck
DFFR
q
Figure 2-14: Logic Symbol
DFFR is a single D‐type register with data input (d), clock (ck), and active‐low reset (rn) inputs
and data (q) output. The active‐low reset input overrides all other inputs when it is asserted
low and sets the data output low. If the asynchronous reset input is not asserted, the data
output is set to the value on the data input upon the next rising edge of the clock.
Pins
Table 2-46: Pin Descriptions
Name Type Description
d Data input.
rn
Active-low asynchronous reset input. A low on rn sets the q output low
independent of the other inputs.
ck Positive-edge clock input.
q
Data output. The value present on the data input is transferred to the q
output upon the rising edge of the clock if the asynchronous reset input is
high.
Parameters
Table 2-47: Parameters
Parameter Defined Values Default Value
init 1’b0
sr_assertion “unclocked”
init
The init parameter defines the initial value of the output of the DFFR register. This is the value
the register takes upon the initial application of power to the FPGA. The default value of the
init parameter is 1’b0.
sr_assertion
The sr_assertion parameter defines the behavior of the output when the sn set input is
asserted. Assigning the sr_assertion to “unclocked” results in an asychronous assertion of the
reset signal, where the q output is set to one upon assertion of the active‐low reset signal.
Assigning the sr_assertion to “clocked” results in a synchronous assertion of the reset signal,
where the q output is set to one at the next rising edge of the clock. The default value of the
sr_assertion parameter is “unclocked”.
input
input
input
output
1’b0, 1’b1
“unclocked”, “clocked”