Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 96
Registers
DFFR
Speedster22i Macro Cell Library
PAGE 80
Table 2-48: Function Table when sr_assertion = “unclocked
Inputs
Output
rn
d
ck
q
’
Table 2-49: Function Table when sr_assertion = “clocked
Inputs
Output
rn
d
ck
q
’
Verilog Instantiation Template
DFFR #(.init(1’b0))
instance_name
(.q(user_out),
.d(user_din),
.rn(user_reset),
.ck(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFR_instance_name : DFFR
generic map (
init => ‘0’)
port map (q => user_out,
d => user_din,
rn => user_reset,
ck => user_clock);
0
X
X
0
1
X
X
Hold
1
0
0
1
1
1
0
X
0
1
X
X
Hold
1
0
0
1
1
1