Heading3 - write_clock_polarity, Heading3 - read_clock_polarity, Heading3 - reg_dout – Achronix Speedster22i User Macro Guide User Manual
Page 175: Heading3 - reg_initval, Heading3 - reg_rstval, Heading3 - regce_priority, Heading3 - mem_init, Heading3 - mem_init_file

Memories
LRAM640
Speedster22i Macro Cell Library
PAGE 158
write_clock_polarity
The write_clock_polarity parameter is used to set the active edge of the wrclk clock. A value of
“rise” corresponds to an active rising edge assignment while “fall” corresponds to an active
falling edge assignment. The default value of the write_clock_polarity parameter is “rise”.
read_clock_polarity
The read_clock_polarity parameter is used to set the active edge of the rdclk clock. A value of
“rise” corresponds to an active rising edge assignment while “fall” corresponds to an active
falling edge assignment. The default value of the read_clock_polarity paramter is “rise”.
reg_dout
The reg_dout parameter defines if the Read Port Output Register is used or bypassed. Setting
reg_dout to 1’b0 bypasses the register while setting reg_dout to 1’b1 enables the register.
Enabling the output register incurrs an additional cycle of latency for the read operation. The
reg_dout parameter defaults to the value 1’b0.
reg_initval
The reg_initval parameter defines the power‐up default value of the Read Port Output
Register. The reg_initval parameter defaults to the value 10’h0.
reg_rstval
The reg_rstval parameter defines the value assigned to the Read Port Output Register when
the rstregn input is asserted low and there is active edge of the rdclk. The reg_rstval parameter
defaults to the value 10’h0.
regce_priority
The regce_priority parameter defines the priority of the outregce clock enable input relative to
the rstregn reset input during an assertion of the rstregn reset input on the Read Port Output
Register. Setting regce_priority to “rstreg” allows the Read Port Output Register to be set/reset
at the next active edge of rdclk without requiring the outregce clock enable input to be active.
Setting regce_priority to “regce” requires that the regce clock enable input is high for the reset
operation to occur at the next active edge of rdclk. The default value of the regce_priority_a
parameter is “rstreg”.
mem_init
The mem_init parameter defines the initial contents of the memory. The 640‐bit parameter
associated with the LRAM640 memory as defined in the
section.
mem_init_file
The mem_init_file parameter provides a mechanism to set the initial contents of the LRAM640
memory. If the mem_init_value is defined, the LRAM640 will be initialized with the values
defined in the file pointed to by the mem_init_file parameter according to the format defined
in the
section. If the mem_init_file is left at the default value
of “”, the initial contents will be defined by the value of the mem_init parameter. If the
memory initialization parameter and the mem_init_file parameters are not defined, the
contents of the LRAM640 will be undefined.