Achronix Speedster22i User Macro Guide - Manual (Page 28)

I/O Cells IOPAD_D2
Speedster Macro Cell Library www.achronix.com PAGE 11
Table 1-13: Parameters
Parameter Defined Values Default Value
location
iostandard “LVCMOS18”
drive
rstmode
rstvalue
slew
keepmode
open_drain “true”, “false” “false”
pvt_comp “none”, “own” “none”
Figure 1-4: IOPAD_D2 Output Timing Diagram (assumes txdata_en = 1’b1)
Figure 1-5: IOPAD_D2 Input Timing Diagram (assumes rxdata_en = 1’b1)
oeclk input Output Enable Register Clock Input.
“” ““
See Table 1‐1
"2", "4", "6", "8", "12", "16" "16"
“sync”, “async” “async”
“low”, “high” “low”
“fast”, “slow” “slow”
"pullup", "pulldown", "none" “none”
Table 1-12: Ports (Continued)
Name Type Description
txclk
dina
dinb
pad
rxclk
douta
doutb
pad