Achronix Speedster22i User Macro Guide - Manual (Page 78)

Registers DFFES
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 62
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFES_instance_name : DFFES
generic map (
init => ‘1’,
sr_assertion => “unclocked”)
port map (q => user_out,
d => user_din,
sn => user_set,
ce => user_clock_enable,
ck => user_clock);