Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template, Verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 80: Vhdl instantiation template
Registers
DFFN
Speedster22i Macro Cell Library
PAGE 64
Verilog Instantiation Template
DFFN #(.init(1’b0))
instance_name
(.q(user_out),
.d(user_din),
.ckn(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFN_instance_name : DFFN
generic map ( init => ‘0’)
port map (q => user_out,
d => user_din,
ckn => user_clock);