Achronix Speedster22i User Macro Guide - Manual (Page 172)

Memories BRAM80KECCFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 155
Parameters
Table 6-47: BRAM80KECCFIFO Parameters
Parameter Defined Values Default Value
sync_mode 1’b0
en_out_reg 1’b1
reg_initval 40’h0
reg_srval 40’h0
reg_rstval 1’b1
regce_priority “rstreg”
wrrst_rstval 1’b1
wrrst_input_mode 2’b10
wrrst_sync_stages 2’b00
wrptr_sync_stages 2’b00
rdrst_rstval 1’b1
rdrst_input_mode 2’b10
rdrst_sync_stages 2’b00
rdptr_sync_stages 2’b00
wrcount_sync_mode 1’b1
rdcount_sync_mode 1’b1
afull_offset 17’h00004
aempty_offset 17’h00004
encoder_enable 1’b1
decoder_enable 1’b1
For a detailed description of the BRAM80KECCFIFO parameters, refer to the like named
parameter desicription given in the BRAM80KFIFO
Parameters and the BRAM80KECC
Parameters sections.
1’b0, 1’b1
1’b0, 1’b1
40-bit hexadecimal number
40-bit hexadecimal number
1’b0, 1’b1
“rstreg”, “regce”
1’b0, 1’b1
2’b00, 2’b01, 2’b10, 2’b11
2’b00, 2’b01, 2’b10, 2’b11
2’b00, 2’b01, 2’b10, 2’b11
1’b0, 1’b1
2’b00, 2’b01, 2’b10, 2’b11
2’b00, 2’b01, 2’b10, 2’b11
2’b00, 2’b01, 2’b10, 2’b11
1’b0, 1’b1
1’b0, 1’b1
17-bit hexadecimal number
17-bit hexadecimal number
1’b0,1’b1
1’b0,1’b1