Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template, Verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 20: Vhdl instantiation template
I/O Cells
IOPAD
Speedster Macro Cell Library
PAGE 3
Verilog Instantiation Template
IOPAD #(.location(""),
.iostandard("LVCMOS18"),
.drive("16"),
.slew("slow"),
.keepmode("none"),
.open_drain("false"),
.hysteresis("none"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.din(user_din), .dout(user_dout), .oe(user_oe),
.pad(user_pad));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
IOPAD_instance_name : IOPAD
generic map (location => "",
iostandard => "LVCMOS18",
drive => "16",
slew => "slow",
keepmode => "none",
open_drain => "false",
hysteresis => "none",
pvt_comp => "none",
termination => "50",
odt => "off")
port map ( din => user_din ,
dout => user_dout ,
oe => user_oe ,
pad => user_pad);