Table - table 1-27: input function table, Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 40
I/O Cells
IPAD_DIFFD
Speedster Macro Cell Library
PAGE 23
Table 1-27: Input Function table
pad
padn
rxdata_en
rxclk
dout
Verilog Instantiation Template
IPAD_DIFFD #( .locationp(""),
.locationn(""),
.iostandard("LVDS"),
.rstmode("async"),
.rstvalue("low"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.pad(user_pad),
.padn(user_padn),
.dout(user_dout),
.rstn(user_rstn),
.data_en(user_data_en),
.clk(user_clk));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
IPAD_DIFFD_instance_name : IPAD_DIFFD
generic map (location => ““,
iostandard => “LVDS”,
rstmode => “async”,
rstvalue => “low”,
pvt_comp => "none",
termination => "50",
odt => "off")
port map (dout => user_dout,
pad => user_pad,
padn => user_padn,
clk => user_clk,
data_en => user_data_en,
rstn => user_rstn);
0
1
1
0
1
0
1
1
X
X
1
X
Z
Z
1
X
X
X
0
Hold previous data
Z
Z
0
Hold previous data