Achronix Speedster22i User Macro Guide - Manual (Page 144)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 127
inputs. Alternatively, the user may also program the reset of the Write Pointer and Read
Pointer independently of each other. For example, the user may program the FIFO reset
inputs to act independently of each other so that the Read Pointer is reset exclusively by the
rdrst input to allow the contents of a previously written FIFO to be reread. Note that as a
result of the Write Pointer reset, the flag outputs are also updated. A block diagram of the
Write Pointer Reset selection circuitry is shown in
Figure 6‐9: Read and Write Pointer Reset
Input Selection Block Diagram . The default value of the wrrst_input_mode parameter is
2’b10.
Table 6-26: wrrst_input_mode Parameter Mapping.
wrrst_input_mode
Selected Input for Write
Pointer Reset
Write Pointer Reset Use Model
2’b00 wrrst input resets Write Pointer Requires wrrst input is synchronous to
wrclk clock domain
2’b01 rdrst input resets Write Pointer Requires rdrst input is synchronous to
wrclk clock domain
2’b10 wrrst or synchronized rdrst
input resets Write Pointer Write pointer may be reset by either
the synchronous wrrst or synchonized
rdrst inputs.
2’b11 Synchronized rdrst input resets
Write Pointer Write Pointer only reset by synchro-
nized rdrst input.
Figure 6-9: Read and Write Pointer Reset Input Selection Block Diagram
Write Reset Synchronizer
d q d q d q d q d q
d q d q d q d q d q
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Read Reset Synchronizer
wrrst
wrclk
rdclk
rdrst
Read
Pointer
Reset
Write
Pointer
Reset
wrrst_input_mode
rdrst_input_mode
wrrst_sync_stages
rdrst_sync_stages