Heading1 - iopad_d2, Figure - figure 1-3: iopad_d2 logic symbol, Iopad_d2 – Achronix Speedster22i User Macro Guide User Manual
Page 26
I/O Cells
IOPAD_D2
Speedster Macro Cell Library
PAGE 9
IOPAD_D2
Bidirectional DDR I/O Pad with Asynchronous or Synchronous Set/
Reset
q
ce
d
rstn
q
ce
d
rstn
srstn
oerstn
douta
pad
Note: For Speedster22iHP, txdata_en and rxdata_en are shared.
For Speedster22iHD, txdata_en and rxdata_en may be driven separately.
IOPAD_D2
q
ce
d
rstn
q
ce
d
rstn
srstn
q
d
rstn
q
d
rstn
q
d
rstn
q
d
rstn
q
d
rstn
q
d
rstn
q
ce
d
rstn
srstn
q
ce
d
rstn
srstn
oe
txclk
txrstn
dina
dinb
txdata_en
txclk
rxdata_en
rxrstn
srstn
rxclk
doutb
Figure 1-3: IOPAD_D2 Logic Symbol
IOPAD_D2 is a Double Data Rate (DDR) I/O pad with active‐high registered output enable.
There is an additional stage of registers on the inputs and outputs to allow the logic level on
the pad to changes on both the rising and falling edges of the clock, but allow the interface
signals to and from the FPGA core to change on the rising edge of the clock. This additional
level of registers provides a full cycle to get into and out of the FPGA core.
P