Heading3 - vhdl instantiation template, Vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 48

I/O Cells
OPAD_D
Speedster Macro Cell Library
PAGE 31
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
OPAD_D_instance_name : OPAD_D
generic map (location => ““,
iostandard => “LVCMOS18”,
drive => "16",
rstmode => “async”,
rstvalue => “low”,
slew => “slow”,
open_drain => "false",
pvt_comp => "none”)
port map (pad => user_pad,
din => user_din,
rstn => user_rstn,
clk => user_clk);