Achronix Speedster22i User Macro Guide - Manual (Page 136)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 119
BRAM80KFIFO
80k-bit FIFO Memory
BRAM80KFIFO dout[31:0]
doutp[3:0]
full
read_err
wrcount[16:0]
din[31:0]
dinp[3:0]
wrrst
rdrst
outregce
dinpx[3:0]
wren
rden
rstreg
doutpx[3:0]
empty
almost_empty
almost_full
write_err
rdcount[16:0]
wrclk
rdclk
Figure 6-7: Logic Symbol
The BRAM80KFIFO implements a 80k‐bit FIFO memory block utilizing the embedded
BRAM80K blocks with dedicated pointer and flag circuitry. The BRAM80KFIFO can be
configured to support a variety of widths and depths, ranging from 2k‐depth with 40‐bit data
down to 64k‐depth with 1‐bit data. The read and write clocks may be either synchronous or
asynchronous with respect to each other. If the user read and write clocks are the same clock,
the user may set the sync_mode to 1’b1 to enable faster and synchronous generation of the
status flags and FIFO pointer outputs.
Figure 6-8: BRAM80KFIFO Block Diagram
BRAM80K
Register
dout,
Memory Write
Pointer
Logic Read
Pointer
Logic
Memory Control /
Flag Generation
Logic
din,
(optional)
wren
wrrst
wrclk
rdrst
rdclk
outregce
rstreg
doutp,
doutpx
dinp,
dinpx
wrcount
rdcount
full
empty
almost_full
almost_empty
write_err
read_err
rden