Table - table 1-52: parameters, Heading3 - verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 63
I/O Cells
TPAD_D
Speedster Macro Cell Library
PAGE 46
Table 1-52: Parameters
Parameter
Defined Values
Default Value
location
iostandard
“LVCMOS18”
drive
rstmode
rstvalue
slew
open_drain
“true”, “false”
“false”
pvt_comp
“none”, “own”
“none”
Table 1-53: Output Function Table (rstmode = “async”)
din
data_en
oe
rstn
clk
pad
Table 1-54: Output Function Table (rstmode = “sync”)
din
data_en
oe
rstn
clk
pad
Verilog Instantiation Template
TPAD_D #(.location(""),
.iostandard("LVCMOS18"),
.drive("16"),
.rstmode("async"),
.rstvalue("low"),
.slew("slow"),
.open_drain("false"),
.pvt_comp("none"))
instance_name (.pad(user_pad), .din(user_din), .oe(user_oe),
.data_en(user_data_en), .rstn(user_rstn), .clk(user_clk));
“
““
See
"2", "4", "6", "8", "12", "16"
"16"
“sync”, “async”
“async”
“low”, “high”
“low”
“fast”, “slow”
“slow”
X
X
X
0
X
Z
X
0
X
1
Hold previous data
X
1
0
1
Z
0
1
1
1
0
1
1
1
1
1
X
1
0
1
Z
X
X
X
0
Z
X
0
X
1
Hold previous data
X
1
0
1
Z
0
1
1
1
0
1
1
1
1
1
X
1
0
1
Z