Achronix Speedster22i User Macro Guide - Manual (Page 73)

Registers DFFER
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 57
DFFER
Positive Clock Edge D-Type Register with Clock Enable and
Asynchronous/Synchronous Reset
rn
ce
d
ck
DFFER
q
Figure 2-5: Logic Symbol
DFFER is a single D‐type register with data input (d), clock enable (ce), clock (ck), and active‐
low reset (rn) inputs and data (q) output. The active‐low reset input overrides all other inputs
when it is asserted low and sets the data output low. The response of the q output in response
to the asserted reset depends on the value of the sr_assertion parameter and is detailed in
Table 2‐15: DFFER Function Table when sr_assertion = “unclocked” and Table
2‐16: DFFER Function Table when sr_assertion = “clocked” . If the reset input is not asserted,
the data output is set to the value on the data input upon the next rising edge of the clock if the
active‐high clock enable input is asserted.
Pins
Table 2-13: Pin Descriptions
Name Type Description
d Data input.
rn
Active-low asynchronous/synchronous reset input. A low on rn sets the
q output low independent of the other inputs if the sr_assertion parame-
ter is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a
low on rn sets the q output low at the next rising edge of the clock.
ce Active-high clock enable input.
ck Positive-edge clock input.
q
Data output. The value present on the data input is transferred to the q
output upon the rising edge of the clock if the clock enable input is high
and the reset input is high.
Parameters
Table 2-14: Parameters
Parameter Defined Values Default Value
init 1’b0
sr_assertion “unclocked”
init
The init parameter defines the initial value of the output of the DFFER register. This is the
value the register takes upon the initial application of power to the FPGA. The default value
of the init parameter is 1’b0.
input
input
input
input
output
1’b0, 1’b1
“unclocked”, “clocked”