Achronix Speedster22i User Macro Guide User Manual
Page 218
PLL/DLL Clock Generators
ACX_CLKGEN
Speedster Macro Cell Library
PAGE 201
CSR_ADDR_DFTADDR
8’h10
0
in/out
Reserved
Reserved
1
in/out
Reserved
Reserved
2
in/out
Reserved
Reserved
3
in/out
Reserved
Reserved
4
in/out
Reserved
Not Used.
5
in/out
Reserved
Not Used.
6
in/out
Reserved
Not Used.
7
in/out
Reserved
Not Used.
CSR_ADDR_PLL_CTL1
8’h11
0
in/out
Reserved
Reserved
1
in/out
Reserved
Reserved
2
in/out
Reserved
Reserved
3
in/out
Reserved
Reserved
4
in/out
Reserved
Reserved
5
in/out
Reserved
Reserved
6
in/out
Reserved
Reserved
7
in/out
Reserved
Reserved
CSR_ADDR_PLL_CTL2
8’h12
0
in/out
Reserved
Reserved
1
in/out
Reserved
Reserved
2
in/out
Reserved
Reserved
3
in/out
Reserved
Reserved
4
in/out
Reserved
Reserved
5
in/out
Reserved
Reserved
6
in/out
Reserved
Reserved
7
in/out
Reserved
Reserved
CSR_ADDR_PLL_CTL3
8’h13
0
in/out
Reserved
Reserved
1
in/out
Reserved
Reserved
2
in/out
Reserved
Reserved
3
in/out
Reserved
Reserved
4
in/out
Reserved
Reserved
5
in/out
Reserved
Reserved
6
in/out
Reserved
Reserved
7
in/out
Reserved
Reserved
CSR_ADDR_PLL_CTL4
8’h14
0
in/out
Reserved
Reserved
1
in/out
Reserved
Reserved
2
in/out
Reserved
Reserved
3
in/out
Reserved
Reserved
4
in/out
Reserved
Reserved
5
in/out
Reserved
Reserved
6
in/out
Reserved
Reserved
7
in/out
Reserved
Reserved
CSR NAME
Addr.
Bit
Type
Initial Value
Description