Achronix Speedster22i User Macro Guide - Manual (Page 208)

PLL/DLL Clock Generators ACX_CLKGEN
Speedster Macro Cell Library www.achronix.com PAGE 191
bypass2 Clkout[2] Bypass.
0: clkout[2] driven by PLL output.
1: clkout[2] driven by refclk input.
1’b0,1’b1 1’b0
bypass3 Clkout[3] Bypass.
0: clkout[3] driven by PLL output.
1: clkout[3] driven by refclk input.
1’b0,1’b1 1’b0
outdiv0 Clkout[0] Rotator / Output Divider Divisor. 6’h1-6’h3F 6’h4
outdiv1 Clkout[1] Rotator / Output Divider Divisor. 6’h1-6’h3F 6’h4
outdiv2 Clkout[2] Rotator / Output Divider Divisor. 6’h1-6’h3F 6’h4
outdiv3 Clkout[3] Rotator / Output Divider Divisor. 6’h1-6’h3F 6’h4
en_phase0 Clkout[0] Phase Shift Enable.
0: Disable phase_inc[0] input.
1: Enable phase_inc[0] input.
1’b0,1’b1 1’b1
en_phase1 Clkout[1] Phase Shift Enable.
0: Disable phase_inc[1] input.
1: Enable phase_inc[1] input.
1’b0,1’b1 1’b1
en_phase2 Clkout[2] Phase Shift Enable.
0: Disable phase_inc[2] input.
1: Enable phase_inc[2] input.
1’b0,1’b1 1’b1
en_phase3 Clkout[3] Phase Shift Enable.
0: Disable phase_inc[3] input.
1: Enable phase_inc[3] input.
1’b0,1’b1 1’b1
static_phase0 Clkout[0] VCO Static Phase Offset. The offset of the clk-
out[0] VCO output in 1/8 ths of the clkout[0] VCO
period.
3’h0-3’h7 3’h0
static_phase1 Clkout[1] VCO Static Phase Offset. The offset of the clk-
out[1] VCO output in 1/8 ths of the clkout[1] VCO
period.
3’h0-3’h7 3’h0
static_phase2 Clkout[2] VCO Static Phase Offset. The offset of the clk-
out[2] VCO output in 1/8 ths of the clkout[2] VCO
period.
3’h0-3’h7 3’h0
static_phase3 Clkout[3] VCO Static Phase Offset. The offset of the clk-
out[3] VCO output in 1/8 ths of the clkout[3] VCO
period.
3’h0-3’h7 3’h0
dyn_phase0 Clkout[0] Dynamic Phase Shift Select. If en_phase0 is
enabled,
0: Clkout[0] phase shift determined by static_phase0
parameter.
1: Clkout[0] phase shift determined from the
number of phase_inc[0] rising edges.
1’b0,1’b1 1’b0
Parameter Description Defined Values
Default
Value