Achronix Speedster22i User Macro Guide - Manual (Page 76)

Registers DFFES
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 60
DFFES
Positive Clock Edge D-Type Register with Clock Enable and
Asynchronous/Synchronous Set
sn
ce
d
ck
DFFES
q
Figure 2-6: Logic Symbol
DFFES is a single D‐type register with data input (d), clock enable (ce), clock (ck), and active‐
low set (sn) inputs and data (q) output. The active‐low set input overrides all other inputs
when it is asserted low and sets the data output high. The resonse of the q output in response
to the asserted set depends on the value of the sr_assertion parameter and is detailed in
Table
2‐19: DFFES Function Table when sr_assertion = “unclocked” and Table 2‐20: DFFES
Function Table when sr_assertion = “clocked” . If the set input is not asserted, the data output
is set to the value on the data input upon the next rising edge of the clock if the active‐high
clock enable input is asserted.
Pins
Table 2-17: Pin Descriptions
Name Type Description
d Data input.
sn
Active-low asynchronous/synchronous set input. A low on sn sets the q
output high independent of the other inputs if the sr_assertion parameter
is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a low
on rn sets the q output high at the next rising edge of the clock.
ce Active-high clock enable input.
ck Positive-edge clock input.
q
Data output. The value present on the data input is transferred to the q
output upon the rising edge of the clock if the clock enable input is high
and the reset input is high.
Parameters
Table 2-18: Parameters
Parameter Defined Values Default Value
init 1’b1
sr_assertion “unclocked”
init
The init parameter defines the initial value of the output of the DFFES register. This is the
value the register takes upon the initial application of power to the FPGA. The default value
of the init parameter is 1’b1.
input
input
input
input
output
1’b0, 1’b1
“unclocked”, “clocked”