Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template, Verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 38: Vhdl instantiation template
I/O Cells
IPAD_DIFF
Speedster Macro Cell Library
PAGE 21
Verilog Instantiation Template
IPAD_DIFF #(.locationp(""),
.locationn(""),
.iostandard("LVDS"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.dout(user_dout),
.pad(user_pad)
.padn(user_padn));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
IPAD_DIFF_instance_name : IPAD_DIFF
generic map (locationp => "",
locationn => "",
iostandard => "LVDS",
pvt_comp => "none",
termination => "50",
odt => "off")
port map (dout => user_dout,
pad => user_pad,
padn => user_padn);
.pad(user_pad));