Heading3 - sr_assertion, Heading3 - verilog instantiation template, Table – Achronix Speedster22i User Macro Guide User Manual
Page 86
Registers
DFFNER
Speedster22i Macro Cell Library
PAGE 70
sr_assertion
The sr_assertion parameter defines the behavior of the output when the rn reset input is
asserted. Assigning the sr_assertion to “unclocked” results in an asychronous assertion of the
reset signal, where the q output is set to zero upon assertion of the active‐low reset signal.
Assigning the sr_assertion to “clocked” results in a synchronous assertion of the reset signal,
where the q output is set to zero at the next falling edge of the clock. The default value of the
sr_assertion parameter is “unclocked”.
Table 2-32: DFFNER Function Table when sr_assertion = “unclocked”
Inputs
Output
rn
ce
d
ckn
q
Table 2-33: DFFNER Function Table when sr_assertion = “clocked”
Inputs
Output
rn
ce
d
ckn
q
Verilog Instantiation Template
DFFNER #(.init(1’b0),
.sr_assertion(“unclocked”))
instance_name
(.q(user_out),
.d(user_din),
.rn(user_reset),
.ce(user_clock_enable),
.ckn(user_clock));
0
X
X
X
0
1
0
X
X
Hold
1
1
0
0
1
1
1
1
0
X
X
0
1
0
X
X
Hold
1
1
0
0
1
1
1
1