Table - table 1-19: input function table, Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 33
I/O Cells
IPAD_D
Speedster Macro Cell Library
PAGE 16
Table 1-19: Input Function table
pad
rxdata_en
rxclk
dout
Verilog Instantiation Template
IPAD_D #( .location(""),
.iostandard("LVCMOS18"),
.rstmode("async"),
.rstvalue("low"),
.keepmode("none"),
.hysteresis("none"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.pad(user_pad),
.dout(user_dout),
.rstn(user_rstn),
.data_en(user_data_en),
.clk(user_clk));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
IPAD_D_instance_name : IPAD_D
generic map (location => ““,
iostandard => “LVCMOS18”,
rstmode => “async”,
rstvalue => “low”,
keepmode => “none”,
hysteresis => "none",
pvt_comp => "none",
termination => "50",
odt => "off")
port map (dout => user_dout,
pad => user_pad,
clk => user_clk,
data_en => user_data_en,
rstn => user_rstn);
0
1
0
1
1
1
X
1
X
Z
1
X
X,Z
0
Hold previous data