Rockwell Automation 20D PowerFlex 700S AC Drives with Phase II Control Programming Manual User Manual
Page 55
Rockwell Automation Publication 20D-PM001C-EN-P - July 2013
55
Programming and Parameters
Chapter 2
254 Opt0/1
RegisCnfg
Configures the registration latch for port 0 of the feedback option card.
• Bits 3 “O0 RLTrgEdg0”, 4 “O0 RLTrgEdg1”, 19 “O1 RLTrgEdg0” and 20 “O1 RLTrgEdg1” select which trigger edges signal the position (see
Table 254A: Edge Selection Settings
• Bits 5 “O0 RL DirRev”, 6 “O0 RL DirFwd”, 21 “O1 RL DirRev” and 22 “O1 RL DirFwd” set the direction of position capture (see
Table 254B: Direction Settings
• Bits 8-11 configure a digital filter for the registration trigger signal. This filter can be used to reject spurious noise. The filter works by waiting a programmed time before deciding that the signal
is valid. This waiting imposes a mandatory delay in the registration signal. The filter delay is programmable in increments of 100 nanoseconds from 0 (or no delay) up to 700 nanoseconds.
255 Opt0/1
RegisCtrl
Configures the registration control on port 0 of the feedback option card.
• Set bits 0 “O0 Arm Req” and 16 “01 Arm Req” to arm the registration logic for the next trigger event. The particular latch will be armed and ready to be strobed on the next occurrence of the
trigger input.
• Set bits 1 “O0 DisarmReq” and 17 “01 DisarmReq” to disarm the registration logic for next trigger event.
After the registration is captured, bit 0 “O0 Arm Req” and bit 16 “O1 Arm Req” automatically resets back to 0 after found. Bit 1 “O0 DisarmReq” and bit 17 “O1 DisarmReq” are only needed to disarm
a registration latch that has not been found yet. Setting bits 1 and 17 will clear the bits 0 and 6. Setting bits 0 and 6 sets bits 0 “Opt0 Armed” and bit 16 “Opt1 Armed” and clears bits 1 “Opt0 Found”
and bit 17 “Opt1 Found” of parameter 256 [Opt0/1 RegisStat].
256 Opt0/1
RegisStat
Indicates the registration control status on port 0 of the feedback option card.
• Bit 0 “Opt0 Armed” indicates the registration latch is armed.
• Bit 1 “Opt0 Found” indicates the registration event has triggered the latch.
• Rising edge of 'Arm request' will set the 'Armed' status bit.
• Rising edge of 'Disarm request' will clear the 'Armed' status bit.
257
Opt 0 Regis Ltch
Displays the registration data of the feedback option card port 0. The registration data is the position reference
counter value latched by the external strobes. The strobe signal used to trigger the latch is configurable by the
[Opt0/1 RegisCnfg].
Default:
Min/Max:
0
-/+2147483648
RO 32-bit
Integer
258
Opt 1 Regis Ltch
Displays the registration data of the feedback option card port 0. The registration data is the position reference
counter value latched by the external strobes. The strobe signal used to trigger the latch is configurable by
[Opt0/1 RegisCnfg].
Default:
Min/Max:
0
-/+2147483648
RO 32-bit
Integer
No.
Name
Description
Values
Link
able
Re
ad
-Write
Da
ta
T
yp
e
Bits 3 & 4, 19 & 20, please refer to Table 254A: Edge Selection Settings below:
Bits 5 & 6, 21 & 22, please refer to
Table 254B: Direction Settings
.
Options
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
O1 R
L D
irF
w
d
O1 R
L D
irR
ev
O1 R
LT
rgE
dg1
O1 R
LT
rgE
dg0
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
RL F
ilt b
it3
RL F
ilt b
it2
RL F
ilt b
it1
RL F
ilt b
it0
Re
ser
ve
d
O0 R
L D
irF
w
d
O0 R
L D
irR
ev
O0 R
LT
rgE
dg1
O0 R
LT
rgE
dg0
Re
ser
ve
d
Re
ser
ve
d
Re
ser
ve
d
Default
x
x
x
x
x
x
x
x
x
0
0
0
0
x
x
x
x
x
x
x
1
0
0
0
x
1
1
0
0
x
x
x
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Table 254A: Edge Selection Settings
Bit 4/20 3/19
0
0
Capture on rising edge
0
1
Capture on falling edge
1
0
Capture on both edges
1
1
Disable capture
Table 254B: Direction Settings
Bit 6/22 5/21
0
0
Disable capture
0
1
Capture position during Reverse rotation
1
0
Capture position during Forward rotation
1
1
Capture position during either rotation
Options
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
O1
Dis
arm
Re
q
O1
Arm
Re
q
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
O0
Dis
arm
Re
q
O0
Arm
Re
q
Default
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Options
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
O
pt1 F
ound
Op
t1
A
rm
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
Re
se
rv
ed
O
pt0 F
ound
Op
t0
A
rm
ed
Default
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True