NEC PD17062 User Manual
Mos integrated circuit, Data sheet
Table of contents
Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- FUNCTION OVERVIEW
- PIN CONFIGURATION (TOP VIEW)
- BLOCK DIAGRAM
- 1. PINS
- 2. PROGRAM MEMORY (ROM)
- 3. PROGRAM COUNTER (PC)
- 4. STACK
- 5. DATA MEMORY (RAM)
- 6. GENERAL-PURPOSE REGISTER (GR)
- 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK
- 8. SYSTEM REGISTER (SYSREG)
- 9. REGISTER FILE (RF)
- 9.1 IDCDMAEN (00H, b1)
- 9.2 SP (01H)
- 9.3 CE (07H, b0)
- 9.4 SERIAL INTERFACE MODE REGISTER (08H)
- 9.5 BTM0MD (09H)
- 9.6 INTVSYN (0FH, b2)
- 9.7 INTNC (0FH, b0)
- 9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)
- 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H)
- 9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H)
- 9.11 TIMER CARRY (17H)
- 9.12 SERIAL INTERFACE WAIT CONTROL (18H)
- 9.13 IEGNC (1FH)
- 9.14 A/D CONVERTOR CONTROL (21H)
- 9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H)
- 9.16 PORT1C I/O SETTING (27H)
- 9.17 SERIAL I/O0 STATUS REGISTER (28H)
- 9.18 INTERRUPT PERMISSION FLAG (2FH)
- 9.19 CROM BANK SELECTION (30H)
- 9.20 IDCEN (31H)
- 9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H)
- 9.22 P1BBIOn (35H)
- 9.23 P0BBIOn (36H)
- 9.24 P0ABIOn (37H)
- 9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE (38H)
- 9.26 SHIFT CLOCK FREQUENCY SETTING (39H)
- 9.27 IRQNC (3FH)
- 10. DATA BUFFER (DBF)
- 11. INTERRUPT
- 11.1 INTERRUPT BLOCK CONFIGURATION
- 11.2 INTERRUPT FUNCTION
- 11.3 INTERRUPT ACCEPTANCE
- 11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE
- 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE
- 11.6 INTERRUPT PROCESSING ROUTINE
- 11.7 EXTERNAL INTERRUPTS (INTNC PIN, V SYNC# PIN)
- 11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE)
- 11.9 MULTIPLE INTERRUPTS
- 12. TIMER
- 13. STANDBY
- 14. RESET
- 15. GENERAL-PURPOSE PORT
- 16. SERIAL INTERFACE
- 17. D/A CONVERTER
- 18. PLL FREQUENCY SYNTHESIZER
- 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION
- 18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK
- 18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER
- 18.4 REFERENCE FREQUENCY GENERATOR (RFG)
- 18.5 PHASE COMPARATOR ( PHI-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK
- 18.6 PLL DISABLE MODE
- 18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER
- 19. A/D CONVERTER
- 20. IMAGE DISPLAY CONTROLLER
- 21. HORIZONTAL SYNC SIGNAL COUNTER
- 22. INSTRUCTION SETS
- 23. RESERVED SYMBOLS FOR ASSEMBLER
- 24. ELECTRICAL CHARACTERISTICS
- 25. PACKAGE DRAWINGS
- 26. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX DEVELOPMENT TOOLS