NEC PD17062 User Manual

Mos integrated circuit, Data sheet

Table of contents

Document Outline

COVER
FEATURES
ORDERING INFORMATION
FUNCTION OVERVIEW
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
1. PINS
- 1.1 PIN FUNCTIONS
- 1.2 EQUIVALENT CIRCUITS OF THE PINS
2. PROGRAM MEMORY (ROM)
- 2.1 CONFIGURATION OF PROGRAM MEMORY
- 2.2 FUNCTIONS OF PROGRAM MEMORY
- 2.3 PROGRAM FLOW
- 2.4 BRANCHING A PROGRAM
- 2.5 SUBROUTINE
- 2.6 TABLE REFERENCE
- 2.7 NOTES ON USING THE BRANCH INSTRUCTION AND SUBROUTINE CALL INSTRUCTION
3. PROGRAM COUNTER (PC)
4. STACK
- 4.1 COMPONENTS
- 4.2 STACK POINTER (SP)
- 4.3 ADDRESS STACK REGISTERS (ASRS)
- 4.4 INTERRUPT STACK REGISTERS
5. DATA MEMORY (RAM)
- 5.1 STRUCTURE OF DATA MEMORY
- 5.2 FUNCTIONS OF DATA MEMORY
- 5.3 NOTES ON USING DATA MEMORY
6. GENERAL-PURPOSE REGISTER (GR)
- 6.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER
- 6.2 FUNCTION OF THE GENERAL-PURPOSE REGISTER
- 6.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS
- 6.4 NOTES ON USING THE GENERAL-PURPOSE REGISTER
7. ARITHMETIC LOGIC UNIT (ALU) BLOCK
- 7.1 OVERVIEW
- 7.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK
- 7.3 ALU OPERATIONS
- 7.4 NOTES ON USING THE ALU
8. SYSTEM REGISTER (SYSREG)
- 8.1 ADDRESS REGISTER (AR)
- 8.2 WINDOW REGISTER (WR)
- 8.3 BANK REGISTER (BANK)
- 8.4 MEMORY POINTER ENABLE FLAG (MPE)
- 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP)
- 8.6 GENERAL-PURPOSE REGISTER POINTER (RP)
- 8.7 PROGRAM STATUS WORD (PSWORD)
9. REGISTER FILE (RF)
- 9.1 IDCDMAEN (00H, b1)
- 9.2 SP (01H)
- 9.3 CE (07H, b0)
- 9.4 SERIAL INTERFACE MODE REGISTER (08H)
- 9.5 BTM0MD (09H)
- 9.6 INTVSYN (0FH, b2)
- 9.7 INTNC (0FH, b0)
- 9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)
- 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H)
- 9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H)
- 9.11 TIMER CARRY (17H)
- 9.12 SERIAL INTERFACE WAIT CONTROL (18H)
- 9.13 IEGNC (1FH)
- 9.14 A/D CONVERTOR CONTROL (21H)
- 9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H)
- 9.16 PORT1C I/O SETTING (27H)
- 9.17 SERIAL I/O0 STATUS REGISTER (28H)
- 9.18 INTERRUPT PERMISSION FLAG (2FH)
- 9.19 CROM BANK SELECTION (30H)
- 9.20 IDCEN (31H)
- 9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H)
- 9.22 P1BBIOn (35H)
- 9.23 P0BBIOn (36H)
- 9.24 P0ABIOn (37H)
- 9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE (38H)
- 9.26 SHIFT CLOCK FREQUENCY SETTING (39H)
- 9.27 IRQNC (3FH)
10. DATA BUFFER (DBF)
- 10.1 DATA BUFFER STRUCTURE
- 10.2 FUNCTIONS OF DATA BUFFER
- 10.3 DATA BUFFER AND TABLE REFERENCING
- 10.4 DATA BUFFER AND PERIPHERAL HARDWARE
- 10.5 DATA BUFFER AND PERIPHERAL REGISTERS
- 10.6 PRECAUTIONS WHEN USING DATA BUFFERS
11. INTERRUPT
- 11.1 INTERRUPT BLOCK CONFIGURATION
- 11.2 INTERRUPT FUNCTION
- 11.3 INTERRUPT ACCEPTANCE
- 11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE
- 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE
- 11.6 INTERRUPT PROCESSING ROUTINE
- 11.7 EXTERNAL INTERRUPTS (INTNC PIN, V SYNC# PIN)
- 11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE)
- 11.9 MULTIPLE INTERRUPTS
12. TIMER
- 12.1 TIMER CONFIGURATION
- 12.2 TIMER FUNCTIONS
- 12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)
- 12.4 CAUTIONS IN USING THE TIMER CARRY FF
- 12.5 TIMER INTERRUPT
- 12.6 CAUTIONS IN USING THE TIMER INTERRUPT
13. STANDBY
- 13.1 STANDBY BLOCK CONFIGURATION
- 13.2 STANDBY FUNCTION
- 13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN
- 13.4 HALT FUNCTION
- 13.5 CLOCK STOP FUNCTION
- 13.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP
14. RESET
- 14.1 RESET BLOCK CONFIGURATION
- 14.2 RESET FUNCTION
- 14.3 CE RESET
- 14.4 POWER-ON RESET
- 14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET
- 14.6 POWER FAILURE DETECTION
15. GENERAL-PURPOSE PORT
- 15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT
- 15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS
- 15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)
- 15.4 GENERAL-PURPOSE INPUT PORT (P0D)
- 15.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)
16. SERIAL INTERFACE
- 16.1 SERIAL INTERFACE MODE REGISTER
- 16.2 CLOCK COUNTER
- 16.3 STATUS REGISTER
- 16.4 WAIT REGISTER
- 16.5 PRESETTABLE SHIFT REGISTER (PSR)
- 16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD)
- 16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)
17. D/A CONVERTER
- 17.1 PWM PINS
18. PLL FREQUENCY SYNTHESIZER
- 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION
- 18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK
- 18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER
- 18.4 REFERENCE FREQUENCY GENERATOR (RFG)
- 18.5 PHASE COMPARATOR ( PHI-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK
- 18.6 PLL DISABLE MODE
- 18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER
19. A/D CONVERTER
- 19.1 PRINCIPLE OF OPERATION
- 19.2 D/A CONVERTER CONFIGURATION
- 19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR)
- 19.4 COMPARISON REGISTER (ADCCMP)
- 19.5 ADC PIN SELECT REGISTER (ADCCHn)
- 19.6 EXAMPLE OF A/D CONVERSION PROGRAM
20. IMAGE DISPLAY CONTROLLER
- 20.1 SPECIFICATION OVERVIEW AND RESTRICTIONS
- 20.2 DIRECT MEMORY ACCESS
- 20.3 IDC ENABLE FLAG
- 20.4 VRAM
- 20.5 CHARACTER ROM
- 20.6 BLANK, R, G, AND B PINS
- 20.7 SPECIFYING THE DISPLAY START POSITION
- 20.8 SAMPLE PROGRAMS
21. HORIZONTAL SYNC SIGNAL COUNTER
- 21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION
- 21.2 GATE CONTROL REGISTER (HSCGT)
- 21.3 HSYNC COUNTER (HSC)
- 21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL
22. INSTRUCTION SETS
- 22.1 OUTLINE OF INSTRUCTION SETS
- 22.2 INSTRUCTIONS
- 22.3 LIST OF INSTRUCTION SETS
- 22.4 BUILT-IN MACRO INSTRUCTIONS
23. RESERVED SYMBOLS FOR ASSEMBLER
- 23.1 SYSTEM REGISTER
- 23.2 DATA BUFFER
- 23.3 PORT REGISTER
- 23.4 REGISTER FILES
- 23.5 PERIPHERAL HARDWARE REGISTER
- 23.6 OTHERS
24. ELECTRICAL CHARACTERISTICS
25. PACKAGE DRAWINGS
26. RECOMMENDED SOLDERING CONDITIONS
APPENDIX DEVELOPMENT TOOLS