NEC PD17062 - Manual (Page 159)

159
µ
PD17062
(2) Cautions in using the P0D 0 /ADC 2 to P0D 3 /ADC 5 pins for an A/D converter
P0D
3
/ADC
5
P0D
2
/ADC
4
P0D
1
/ADC
3
P0D 0 /ADC 2
A/D input
A/D input Latch
General-purpose port
If one of the P0D
0
/ADC
2
to P0D
3
/ADC
5
pins is selected for an A/D converter (only one pin can be selected
at one time), it is disconnected from the input latch and connected to the internal A/D converter input.
If a pin happens to be at a high level when it is selected for an A/D converter, the latch circuit is held at
a high.
If the HALT 0001B instruction is executed under the above condition, the halt state is released immediately
because the input latch is at a high.
To solve the above problem, specify the input port so that a low level is input to the A/D converter, before
executing the HALT 0001B instruction.