NEC PD17062 - Manual (Page 276)

276
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PD17062
21.3 HSYNC COUNTER (HSC)
The HSYNC counter is mapped at peripheral address 04H. It is a 6-bit read-only binary counter. It can be
read-accessed through the data buffer using the GET instruction.
When it overflows, the 6-bit HSYNC counter goes back to 00H.
The HSYNC counter is reset to 00H at a power-on reset and clock stop.
(1) Gate open bit (HSCGOSTT)
The HSCGOSTT is mapped at the MSB (b
3
) of the register file at 12H. It is always high when the gate with
the Hsync input is open. Note that when the 1.69 ms gate mode is selected, the HSCGOSTT becomes high
when the input data is set even if there is no gate clock.
21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL
The following example is a program that uses the horizontal sync signal counter.
When the 1.69 ms gate is open
CLR1 P0BBIO3 ; Sets P0B3 in input mode.
PEEK WR, 0B6H
AND WR, #0111B
POKE 0B6H, WR
LOOP:
PEEK WR, #92H ; Makes sure that the gate is closed once.
SKF WR, #1000B
BR LOOP
;
MOV WR, #0010B ; Selects the 1.69 ms gate mode.
POKE 91H, WR
LOOP2:
PEEK WR, #92H ; Makes sure that the gate is closed.
SKF WR, #1000B
BR LOOP2
GET DBF, HSC ; Reads the content of the HSYNC counter.
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