NEC PD17062 - Manual (Page 115)

115
µ
PD17062
Fig. 11-3 Interrupt Acceptance Timing Chart
(2) When two or more interrupts (e.g., rising edge at the INT NC pin and falling edge at the V SYNC pin) are used
(a) Hardware priorities
(b) Software priorities
Instruction EI
MOV
WR, #0101B
POKE
INTPM, WR
INTE
INT NC pin
IRQVSYN flag
IPNC flag
EI
IPVSYN flag
IRQNC flag
V
SYNC
pin
Interrupt
cycle
Interrupt
cycle
V SYNC pin interrupt acceptance
INT NC pin interrupt holding period INT NC pin interrupt processing V SYNC pin
interrupt processing
V SYNC pin interrupt holding period
INT NC pin interrupt acceptance
Instruction EI
MOV
WR, #0100B
POKE
INTPM, WR
INTE
INT
NC
pin
IRQNC flag
IPNC flag
EI
IPVSYN flag
IRQNC flag
V SYNC pin
MOV
WR, #0101B
POKE
INTPM, WR
INT NC pin interrupt holding period
V SYNC pin interrupt acceptance
INT NC pin interrupt
processing
INT NC pin interrupt acceptance
V
SYNC
pin interrupt holding period V SYNC pin interrupt processing
Interrupt
cycle Interrupt
cycle