NEC PD17062 - Manual (Page 228)

228
µ
PD17062
18.5.3 Charge Pump
As shown in Fig. 18-5, the charge pump directs the up request signal (UP) or down request signal (DW)
from the phase comparator (
φ
-DET) to the error output pin (EO) pin.
The relationships among the output at the error output pin, divider output frequency f
N
, and reference
frequency f r are as follows:
Reference frequency f r > divider output frequency f N : Low level output
Reference frequency f
r
< divider output frequency f
N
: High level output
Reference frequency f r = divider output frequency f N : Floating
18.5.4 Unlock Detection Block
As shown in Fig. 18-5, the unlock detection block detects the unlock state of the PLL frequency synthesizer
according to the up request signal (UP) or down request signal (DW) from the phase comparator (
φ
-DET).
Either the up or down request signal is low in the unlock state. So the unlock detection block detects this
low signal as unlock state. When the unlock state is detected, the unlock flip-flop (FF) is set (1).
The state of the unlock FF is detected using the PLL unlock FF judge register (at address 22H).
The unlock FF is set at intervals of the then selected reference frequency f
r
.
The unlock FF is reset when the PLL unlock FF judge register is read-accessed with a PEEK instruction.
The unlock FF must be checked at intervals greater than the period (1/f r ) of the reference frequency f r .
The unlock delay control circuit controls whether to set the unlock FF, by delaying the up and down request
signals output from the phase comparator.
If the delay becomes large, the unlock FF will not be set even if the phase difference between the divider
output frequency f
N
and reference frequency fr is large.
The delay is specified in the unlock delay control circuit using the PLL unlock FF delay control register (at
address 32H).
The following paragraphs describe the configuration and functions of the PLL unlock FF judge register and
PLL unlock FF delay control register.