NEC PD17062 - Manual (Page 121)

121
µ
PD17062
11.7 EXTERNAL INTERRUPTS (INT NC PIN, V SYNC PIN)
There are two external interrupt sources: INT NC and V SYNC .
An interrupt request is issued when a rising or falling edge is input to the INT NC or V SYNC pin.
11.7.1 Configuration
Fig. 11-5 shows the configurations of the INT
NC
and V
SYNC
interrupts.
As shown in Fig. 11-5, the INT NC and V SYNC signals are input to the INTNC or INTVSYN latch and to edge
detectors.
The edge detectors output their respective interrupt request signals according to the inputs from the pin
and the status of the IEGNC or IEGVSYN flip-flop.
The IEGNC flip-flop and IEGVSYN flip-flop correspond to the IEGNC flag and IEGVSYN flag, respectively,
in the interrupt edge selection register (INTEDGE: address 1FH) of the control register.
The INTNC latch and INTVSYN latch correspond to the INTNC flag and INTVSYN flag, respectively, in the
interrupt-pin-level judge register (INTJDG: address 0FH) of the control register.
The Schmitt triggers at the INT
NC
and V
SYNC
inputs prevent pulses operations due to noise. These pins do
not accept pulses of 1
µ
s or less.
A minimum pulse width can be set for the INT
NC
pin. See Section 9.10.
Fig. 11-5 INT 0 Pin and INT 1 Pin Configurations
IRQNC
IRQVSYN
INTNC latch
INTVSYN latch
IEGVSYN flip-flop
0 FH 1 FH
b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0
0
I
E
G
V
S
Y
N
0
I
E
G
N
C
0
I
N
T
V
S
Y
N
0
I
N
T
N
C
Control register
Name
Address
Bit
Flag
symbol
Interrupt
edge select
(INTEDGE)
Interrupt
pin level judge
(INTJDG)
V
SYNC
pin
INT
NC
pin
Schmitt trigger
IEGNC flip-flop
Edge detection
Interrupt request block
Edge detection
Schmitt trigger