NEC PD17062 User Manual
Page 114
114
µ
PD17062
Fig. 11-3 Interrupt Reception Timing Chart (1/2)
(1) When one interrupt (e.g., rising edge at the INT
NC
pin) is used
(a) When an interrupt mask time is not set by the interrupt permission flag
#
# When the MOVT instruction or a normal instruction that does not satisfy the skip conditions is
executed at interrupt acceptance
$
$ When the MOVT instruction or an instruction satisfying the skip conditions is executed at
interrupt reception
(b) When an interrupt holding period is set by the interrupt permission flag
Instruction
EI
MOV
WR, #0001B
POKE
INTPM, WR
INTE
INT
NC
pin
IRQNC flag
IPNC flag
Interrupt acceptance
Normal
instruction
Interrupt
cycle
or 12 s
1 instruction cycle:
2 s
Interrupt permission
period
Interrupt processing
routine
µ
µ
Instruction
EI
MOV
WR, #0001B
POKE
INTPM, WR
INTE
INT
NC
pin
IRQNC flag
IPNC flag
Interrupt processing
routine
MOVT DBF,
@AR skip
instruction
Interrupt
cycle
Interrupt acceptance
Instruction
EI
MOV
WR, #0001B
POKE
INTPM, WR
INTE
INT
NC
pin
IRQNC flag
IPNC flag
Interrupt acceptance
Interrupt
cycle
Interrupt holding period
Interrupt processing
routine