NEC PD17062 - Manual (Page 84)

84
µ
PD17062
9.20 IDCEN (31H)
9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H)
b 3 b 2 b 1 b 0
0 0 IDCEN
31H
0
1
0
IDC operation prohibited (display off)
IDC operation start (display on)
b
3
b
2
b
1
b
0
PLULSEN3
32H
0
0
1
1
0
1
0
1
PLULSEN2 PLULSEN1 PLULSEN0
1.25 to 1.5 s or more
3.5 to 3.75 s or more
0.25 to 0.5 s or more
Unlock flip-flop disable (always set)
Fixed at 0
Setting of the delay time of the reference frequency f r and
divided frequency f N required for setting the unlock flip-flop
µ
µ
µ