NEC PD17062 - Manual (Page 243)

243
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PD17062
20.2 DIRECT MEMORY ACCESS
The direct memory access (DMA) function transfers memory contents directly to peripheral equipment,
without using the CPU.
In the
µ
PD17062, the DMA mode is used to run the IDC.
The instruction cycle of the
µ
PD17062 is 2
µ
s, but its apparent instruction cycle becomes 12
µ
s during the
DMA mode. This does not mean that the actual instruction cycle becomes 12
µ
s, but means that data transfer
for the IDC takes 10
µ
s (5 instruction cycles) and execution of an instruction takes one instruction cycle as usual.
During DMA mode, instructions are executed at every five instruction cycles.
For the above reason, execution of one instruction takes 12
µ
s apparently when the IDC is being used. In
a program in which a problem may occur if 12
µ
s and 2
µ
s instruction cycles are mixed, the IDC must be kept
at a stop and the DMA mode can be specified only for critical sections of the program. In this case, during
five instruction cycles for IDC data transfer, only the clock operates, and the
µ
PD17062 does nothing.
During the DMA mode, the ROM address for five instructions out of the six is not pointed to by the program
counter. Instead, it is pointed to by the CROM address pointer, and the RAM address is pointed to by the VRAM
address pointer.
The DMA mode is controlled using the IDCDMAEN flag.
The IDCDMAEN flag is mapped at the register file. It is a one-bit flag that can be both read- and write-
accessed. When this flag is set, a DMA request is accepted to begin the DMA mode in preference to any other
interrupt request. When the IDCDMAEN flag is reset, no DMA request is accepted. If it is reset during the
DMA mode, the DMA mode is terminated upon completion of the instruction that resets the flag.
Table 20-1 IDCDMAEN Flag
0 0 IDCDMAEN 0
b 3 b 2 b 1 b 0
0
0
Does not use the DMA mode (instruction cycle: 2 s )
Uses the DMA mode (instruction cycle: 12 s ).
(RF 00H)
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