NEC PD17062 - Manual (Page 71)

71
µ
PD17062
Table 9-1 Peripheral Hardware Control Functions of Control Registers (2/5)
Remark *: Retains the previous state.
Peripheral hardware
Control register Peripheral hardware control function At reset
Register Ad-
dress Read/
write
b3
b2
b1
b0
Symbol Function outline
Set value
0 1
P
o
w
e
r
O
n
S
T
O
P
C
E
Interrupt
Pin
PLL frequency synthesizer
Interrupt edge
select register
Interrupt
permission
register
Interrupt
request
register
CE pin level
judge register
PLL reference
clock select
register
PLL unlock
flip-flop judge
register
PLL unlock
flip-flop
sensibility
select register
1FH R/W
2FH R/W
3FH R
07H R
13H R/W
22H R
32H R/W
0
IEGVSYN
0
IEGNC
IPVSYN
IPSIO0
IPBTM0
IPNC
IRQVSYN
IRQSIO0
IRQBTM0
IRQNC
0
0
0
CE
PLLRFCK3
PLLRFCK2
PLLRFCK1
PLLRFCK0
0
0
0
PLLUL
0
0
PLULSEN1
PLULSEN0
Fixed at 0
Sets the interrupt issue edge (V
SYNC
)
Fixed at 0
Sets the interrupt issue edge (INT
NC
)
- Serial interface 0
- V SYNC signal
- Basic timer 0
- INT NC pin
- Serial interface 0
- V
SYNC
signal
- Basic timer 0
- INT NC pin
Sets
the in-
terrupt
permis-
sion of:
Sets
the in-
terrupt
request
of:
Fixed at 0
Detects the CE pin state
Fixed at 1
Fixed at 0
Detects the unlock flip-flop state
Fixed at 0
Sets the set delay time for
the unlock flip-flop
Rising edge Falling edge
Rising edge Falling edge
0 0 0
0 1 1
Interrupt
disabled Interrupt
enabled
No interrupt
request/
processing
in progress
Interrupt
request made
0 0 0
Low level High Level
0 – –
2: 6.25 kHz 3: 12.5 kHz
6: 25 kHz
F: Operation stopped (disabled state)
0, 1, 4, 5, 7-E: Setting disabled
Locked state Unlocked state
0 0 1 1
0 1 0 1
1.25 3.5 0.25
1.5 s 3.75 s 0.5 s
µ µ µ
Disabled
state
to to to
F F *
0 * *
0 0 *