NEC PD17062 - Manual (Page 7)

7
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PD17062
8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ...................... 57
8.6 GENERAL-PURPOSE REGISTER POINTER (RP) .......................................................................... 66
8.7 PROGRAM STATUS WORD (PSWORD) ...................................................................................... 66
9. REGISTER FILE (RF) ................................................................................................................... 67
9.1 IDCDMAEN (00H, b
1
) ...................................................................................................................... 75
9.2 SP (01H) ........................................................................................................................................... 75
9.3 CE (07H, b
0
) ..................................................................................................................................... 76
9.4 SERIAL INTERFACE MODE REGISTER (08H) .............................................................................. 76
9.5 BTM0MD (09H) ............................................................................................................................... 77
9.6 INTVSYN (0FH, b 2 ) ......................................................................................................................... 77
9.7 INTNC (0FH, b 0 ) .............................................................................................................................. 78
9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H) .......................... 78
9.9 PLL REFERENCE MODE SELECTION REGISTER (13H) .............................................................. 79
9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H) .................................................. 79
9.11 TIMER CARRY (17H) ....................................................................................................................... 80
9.12 SERIAL INTERFACE WAIT CONTROL (18H) ................................................................................ 80
9.13 IEGNC (1FH) .................................................................................................................................... 80
9.14 A/D CONVERTOR CONTROL (21H) .............................................................................................. 81
9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H) ..................................................................... 81
9.16 PORT1C I/O SETTING (27H) .......................................................................................................... 82
9.17 SERIAL I/O0 STATUS REGISTER (28H) ....................................................................................... 82
9.18 INTERRUPT PERMISSION FLAG (2FH) ........................................................................................ 83
9.19 CROM BANK SELECTION (30H) ................................................................................................... 83
9.20 IDCEN (31H) .................................................................................................................................... 84
9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) .................................................. 84
9.22 P1BBIOn (35H) ................................................................................................................................ 85
9.23 P0BBIOn (36H) ................................................................................................................................ 85
9.24 P0ABIOn (37H) ................................................................................................................................ 86
9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN
SERIAL INTERFACE MODE (38H) ................................................................................................. 86
9.26 SHIFT CLOCK FREQUENCY SETTING (39H) ............................................................................... 87
9.27 IRQNC (3FH) .................................................................................................................................... 87
10. DATA BUFFER (DBF) .................................................................................................................. 88
10.1 DATA BUFFER STRUCTURE ......................................................................................................... 88
10.2 FUNCTIONS OF DATA BUFFER .................................................................................................... 90
10.3 DATA BUFFER AND TABLE REFERENCING ................................................................................ 91
10.4 DATA BUFFER AND PERIPHERAL HARDWARE ......................................................................... 93
10.5 DATA BUFFER AND PERIPHERAL REGISTERS .......................................................................... 97
10.6 PRECAUTIONS WHEN USING DATA BUFFERS ......................................................................... 104
11. INTERRUPT ................................................................................................................................. 106
11.1 INTERRUPT BLOCK CONFIGURATION ........................................................................................ 106
11.2 INTERRUPT FUNCTION ................................................................................................................. 108
11.3 INTERRUPT ACCEPTANCE ............................................................................................................ 111
11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE ...................................................................... 116