NEC PD17062 User Manual
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PD17062
14.6.2 Cautions at Power Failure Detection with BTM0CY Flag
When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the
following points.
(1) Clock updating
When writing a clock program by using the timer carry FF, the clock must be updated after a power failure.
This is because the BTM0CY flag is reset to 0 and one clock count is lost by BTM0CY flag reading when
a power failure is detected.
(2) Clock update processing time
When the clock is updated, its processing must end before the next rising edge of the timer carry FF set
pulse.
This is because if the CE pin rises to high level during clock update processing, the clock update processing
will not be executed up to the end and a CE reset will be applied.
For (1) and (2) above, see Section 12.4.2.
When processing is performed at a power failure, careful attention must be given to the following point.
(3) Power failure detection timing
When clock counting, etc. is performed with the BTM0CY flag, the flag must be read for power-failure
detection before the next rising edge of the timer carry FF set pulse, after a program starts from address
0000H.
This is because when the timer carry FF set time is set to 5 ms, for instance, and power failure detection
is performed 6 ms after the program starts, one BTM0CY flag is lost.
See Section 12.4.2.
As shown in the example on the next page, power failure detection and initialization must be performed
within the timer carry FF set time.
This is because when the CE pin is raised and CE reset is applied during power failure processing and
initialization, these processings are interrupted and a problem may occur.
When the timer carry FF set time is changed in initialization, an instruction that makes the change must
be executed at the end of initialization.
This is also because when the timer carry FF set time is switched before initialization as shown in the
example on the next page, initialization by CE reset may not be executed up to the end.