NEC PD17062 - Manual (Page 81)

81
µ
PD17062
b
3
b
2
b
1
b
0
ADCCH2 ADCCH1 ADCCMP
21H
ADCCH0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
ADC 0 select
ADC
1
select, shared with P1C
3
ADC
2
select, shared with P0D
0
ADC 3 select, shared with P1D 1
ADC
4
select, shared with P0D
2
ADC 5 select, shared with P0D 3
No corresponding channel
(not to be set)
A/D converter input channel select
9.14 A/D CONVERTOR CONTROL (21H)
9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H)
b
3
b
2
b
1
b
0
0 0 PLLUL
22H
0
1
0
Detects the unlock flip-flop state
Unlock flip-flop = 0: PLL locked
Unlock flip-flop = 1: PLL unlocked