NEC PD17062 - Manual (Page 229)

229
µ
PD17062
(1) PLL unlock FF judge register (PLLULJDG)
This register is a read-only register. It is reset when its content is read into a window register (WR) with
a PEEK instruction.
Because the unlock FF is set at intervals of the period (1/f
r
) of the reference frequency f
r
, the content of
this register must be read into the window register at intervals larger than the period of the reference
frequency.
Fig. 18-7 Configuration and Functions of the PLL Unlock FF Judge Register (PLLULJDG)
Remark The PLLULJDG is reset when it is read-accessed with a PEEK instruction.
Register
Flag symbol
b 3 b 2 b 1 b 0
P
L
L
U
L
22H R
Address Read/write
Upon reset
Power-on
Clock stop
CE
0 0
0
1
Detects the state of the unlock FF.
Unlock FF = 0 : PLL locked
Unlock FF = 1 : PLL unlocked
0 *
0
Fixed to 0.
PLL unlock FF
judge register
(PLLULJDG)
0 0
* Undefined
Hold
Hold