NEC PD17062 User Manual
Page 210
210
µ
PD17062
Table 16-8 Wait Timings
(1) Slave operation wait in two-wire bus mode
When the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the SCL pin is switched to output mode
and a low level signal is output.
If no-wait (SIO0WRQ1 = SIO0WRQ0 = 0) is specified, this operation is not performed.
Wait is released by writing 1 into the SIO0NWT flag of the wait register.
For example, if 1 is written into the SIO0NWT flag of the wait register while waiting with the data wait
mode (SIO0WRQ1 = 0, SIO0WRQ0 = 1: Waits when the shift clock falls with the clock counter set to 8)
specified, wait is released. When the shift clock falls with the clock counter set to 8 again, the slave
operation waits again.
If communication has not started in slave operation, ordinary address wait mode (SIO0WRQ1 = SIO0WRQ0
= 1) is specified. In this wait mode, the slave operation waits when the shift clock falls, with the clock
counter at set to 8, the first time after detection of the start condition. This means that, in this mode, the
slave operation waits before the ninth clock (for acknowledgment of transmission of the slave address)
rises. While the slave operation waits in this mode, the contents of the presettable shift register (PSR)
are read to determine whether the address is mapped to the local station.
Testing the SIO0NWT flag enables the system to determine whether the slave operation is waiting.
SIO0WRQ1
SIO0WRQ0
Wait mode
Two-wire bus mode
Serial I/O mode
0
0
No-wait
Does not wait.
Does not wait.
0
1
Data wait
Waits when the shift clock falls
Waits with the shift clock in the
with the clock counter set to 8.
high level state when the contents
of the clock counter become 8.
1
0
Acknowledge wait
Waits when the shift clock falls
Waits with the shift clock in the
with the clock counter set to 9.
high level state when the contents
of the clock counter become 9.
1
1
Address wait
Waits when the shift clock falls
Not to be set
with the clock counter set to 8
after detection of the start
condition.