NEC PD17062 - Manual (Page 69)

69
µ
PD17062
Fig. 9-1 Configuration of Control Register (2/2)
8 9 A B C D E F
S
I
O
0
C
H
S
B S
I
O
0
M
S
S
I
O
0
T
X
B
T
M
0
C
K
0
0
I
N
T
V
S
Y
N
I
N
T
N
C
R/W R/W
0
I
E
G
V
S
Y
N
I
E
G
N
C
B
T
M
0
Z
X
R
S
B
A
C
K S
I
O
0
N
W
T
S
I
O
0
W
R
Q
1
S
I
O
0
W
R
Q
0
R/W R/W
S
I
O
0
S
F
8
S
I
O
0
S
F
9
S
B
S
T
T S
B
B
S
Y I
P
N
C
R R/W
0
S
I
O
0
I
M
D
0
0
S
I
O
0
I
M
D
1
0 0
S
I
O
0
C
K
1
S
I
O
0
C
K
0
I
R
Q
S
I
O
0
I
R
Q
N
C
R/W R/W R
Serial I/O0
mode select
register
Timer 0
clock select
register
Interrupt-
level judge
register
Serial I/O0
wait control
register
Interrupt
edge
selection
register
Serial I/O0
status judge
register
Interrupt
enable
register
Serial I/O0
interrupt
mode register
Serial I/O0
clock select
register
Interrupt
request
register
B
T
M
0
C
K
1
B
T
M
0
C
K
2
0
0
I
P
V
S
Y
N
I
P
B
T
M
0
I
R
Q
B
T
M
0
I
R
Q
V
S
Y
N
I
P
S
I
O
0