NEC PD17062 - Manual (Page 9)

9
µ
PD17062
17. D/A CONVERTER ....................................................................................................................... 217
17.1 PWM PINS ....................................................................................................................................... 217
18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 219
18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION ................................................................. 219
18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK .............................................. 220
18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER ................................... 221
18.4 REFERENCE FREQUENCY GENERATOR (RFG) .......................................................................... 223
18.5 PHASE COMPARATOR (
φ
-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK ......... 225
18.6 PLL DISABLE MODE ....................................................................................................................... 231
18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER .................................................... 232
19. A/D CONVERTER ....................................................................................................................... 233
19.1 PRINCIPLE OF OPERATION ........................................................................................................... 233
19.2 D/A CONVERTER CONFIGURATION ........................................................................................... 234
19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR) ................................................................ 235
19.4 COMPARISON REGISTER (ADCCMP) .......................................................................................... 235
19.5 ADC PIN SELECT REGISTER (ADCCHn) ...................................................................................... 236
19.6 EXAMPLE OF A/D CONVERSION PROGRAM ............................................................................ 237
20. IMAGE DISPLAY CONTROLLER ............................................................................................... 240
20.1 SPECIFICATION OVERVIEW AND RESTRICTIONS .................................................................... 240
20.2 DIRECT MEMORY ACCESS ........................................................................................................... 243
20.3 IDC ENABLE FLAG ......................................................................................................................... 245
20.4 VRAM ............................................................................................................................................... 246
20.5 CHARACTER ROM .......................................................................................................................... 255
20.6 BLANK, R, G, AND B PINS ............................................................................................................ 263
20.7 SPECIFYING THE DISPLAY START POSITION ........................................................................... 264
20.8 SAMPLE PROGRAMS .................................................................................................................... 268
21. HORIZONTAL SYNC SIGNAL COUNTER ................................................................................ 274
21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION .................................................... 274
21.2 GATE CONTROL REGISTER (HSCGT) .......................................................................................... 275
21.3 HSYNC COUNTER (HSC) ............................................................................................................... 276
21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL .......................................................... 276
22. INSTRUCTION SETS .................................................................................................................. 277
22.1 OUTLINE OF INSTRUCTION SETS ............................................................................................... 277
22.2 INSTRUCTIONS .............................................................................................................................. 278
22.3 LIST OF INSTRUCTION SETS ....................................................................................................... 279
22.4 BUILT-IN MACRO INSTRUCTIONS .............................................................................................. 281
23. RESERVED SYMBOLS FOR ASSEMBLER ............................................................................... 282
23.1 SYSTEM REGISTER (SYSREG) ..................................................................................................... 282
23.2 DATA BUFFER (DBF) ...................................................................................................................... 282
23.3 PORT REGISTER ............................................................................................................................. 283
23.4 REGISTER FILES ............................................................................................................................. 284